This invention relates to a method of designing a semiconductor integrated circuit, which may be effectively applicable, for instance, to designing full-custom LSI (large-scale integrated circuit) for specific uses.
The investigation of characteristics LSI is discussed in CICC (1987), pp. 133 to 136. According to this paper, the characteristics are evaluated by determining the wiring resistances and capacitances of a detailed wiring pattern prepared beforehand.
A method for setting a layout of elements in an LSI is described in a Japanese Patent Application which was laid open to public inspection on Feb. 20, 1987 under Provisional Publication No. 39024/87. According to this method, first the layout of elements is set tentatively, and then tentative wiring routes are set. In accordance with theoretical lengths of wirings based on the tentative wiring routes, signal delays are estimated, and the results of this estimate are reflected on the layout of elements. It is disclosed in the above method employing the tentative wiring routes that a technique such as the Steiner tree method is adopted.
Additionally, there is described a method of establishing roundabout routes by setting turning points.
Before the actual wiring pattern of an LSI, it is necessary to prepare a detailed wiring pattern (including the examination of through holes etc.) and check its characteristics. The preparation of such a detailed wiring pattern requires many man-hours because it must meet all required electrical and physical conditions, including layout rules. Accordingly, the problem with the above-described method is that the man-hours taken to design an LSI greatly increases if a detailed wiring pattern is prepared repeatedly until desired results are obtained at the investigation of characteristics.
It is necessary, therefore, to estimate the characteristics of the detailed wiring pattern prior to the preparation thereof. To this end, a tentative wiring pattern for the investigation of characteristics must be prepared. Such a tentative pattern is required to closely resemble the final wiring pattern in order to accurately estimate the final characteristics. However, an attempt to make it too close to the final pattern involves increased man-hours so that the total design costs for an LSI cannot be reduced.